Circuit Designs for Low-power and Seu- Hardened Systems Circuit Designs for Low-power and Seu- Hardened Systems Vii Circuit Designs for Low-power and Seu-hardened Systems
نویسندگان
چکیده
OF THESIS Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science Electrical Engineering The University of New Mexico Albuquerque, New Mexico
منابع مشابه
Low Power Dissipation SEU-hardened CMOS Latch
This paper reports three design improvements for CMOS latches hardened against single event upset (SEU) based on three memory cells appeared in recent years. The improvement drastically reduces static power dissipation, reduces the number of transistors required in the VLSI, especially when they are used in the Gate Array. The original cells and the new improved latches are compared. It is show...
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